Proceso de diseño de PCB HDI explicado en detalle

Detailed Breakdown of the Complete HDI PCB Design Process

1. Requirement Analysis and Pre-Design Preparation

Core Objective

Convert abstract requirements into actionable design specifications and confirm manufacturing feasibility.

Detailed Execution Process

Requirement Investigation (Sub-Steps)

• Confirmation with Product Team:
  Escenarios de aplicación (Electrónica de consumo / médico / industrial), operating environment (temperatura / humedad / vibración), product lifecycle (≥5 years requires enhanced reliability)

• Confirmation with Hardware Engineers:
  Core IC models (P.EJ., BGA package parameters), power architecture (niveles de voltaje / current requirements), signal types (de alta velocidad / analog / digital)

• Preliminary Communication with PCB Manufacturer:
  Confirm manufacturing limits (minimum laser via diameter / maximum layer count / impedance control capability)

Requirement Document (SOR) Preparation (Deliverable)

Tools and Resource Preparation (Sub-Steps)

• Design Software Setup:
  Install corresponding plugins (Altium → HDI Toolkit; Cadence → Microvia Optimizer), import manufacturer process libraries (IPC-2226A standard templates)

• Reference Material Collection:
  Core IC datasheets (focus on package pinout and power requirements), manufacturer process specifications (laser drilling parameters / lamination process), estándares de la industria (IPC-6012E)

• Process Gate Decision:
  Proceed to the next step only after SOR document approval and manufacturer process feasibility confirmation (manufacturer must issue a Process Compatibility Confirmation Letter).

2. Stack-Up Design

Stack-Up Design

Core Objective

Define layer structure, blind/buried via distribution, and impedance control strategy to enable subsequent routing.

Detailed Execution Process

Stack-Up Layer Count Determination (Sub-Steps)

• Signal Layer Estimation:
  Calculate required signal layers based on critical signals (de alta velocidad / differential).
  Follow the principle: one signal layer corresponds to one reference layer.
  Ejemplo: 8 Pítico 4.0 differential pairs → 4 signal layers + 4 reference layers = 8 capas

• Power/Ground Layer Allocation:
  Divide by voltage domains (P.EJ., 3.3 V / 1.8 V / core voltage).
  Each major voltage domain requires at least one power layer and one adjacent ground layer.

• Blind/Buried Via Layer Matching:
  If blind vias are required for “Top → L2” and “L7 → Bottom”, and buried vias for “L3 → L6”, the stack-up must be:
  Arriba (S1) – L2 (S2) – L3 (P1) – L4 (G1) – L5 (G2) – L6 (P2) – L7 (S3) – Bottom (S4)

Stack-Up Parameter Design (Sub-Steps)

• Layer Thickness Allocation:
  Standard combination: signal layer 0.07 mm + dielectric 0.1 mm + power layer 0.1 mm
  Example total thickness 1.6 mm:
  0.07 × 4 + 0.1 × 3 + 0.1 × 1 = 1.6 mm

• Impedance Simulation and Validation:
  Use Ansys SIwave, input layer thickness and Dk values, simulate single-ended and differential impedance.
  Adjust dielectric thickness if impedance deviates (P.EJ., increase dielectric thickness if impedance is too low).

• Blind/Buried Via Path Planning:
  Draw via connection diagrams (P.EJ., S1→S2 blind via, S3→S4 blind via, L3→L6 buried via) to avoid via overlap.

Stack-Up Design Deliverables

• Stack-up structure drawing (layer thickness / materiales / via types)

• Impedance simulation report

• Blind/buried via distribution table

Process Gate Criteria:
Impedance error ≤ ±3%, blind/buried via aspect ratio ≤ 0.75:1, layer-to-layer alignment meets manufacturer requirements (within ±25 μm).

3. Component Selection and Placement Design

Component Selection and Placement Design

ution Process (Placement Order)

Component Selection Confirmation (Pre-Step)

• Package Priority:
  Prefer 0201 / 01005 paquetes (confirm SMT capability); core ICs prioritize BGA/CSP packages to reduce footprint.

• Material Compatibility Check:
  Confirm pin pitch (≥0.4 mm for routing feasibility), power dissipation (≤2 W per component; higher requires thermal design).

Placement Execution Steps

• Fix Core Components:
  Place CPU/GPU/FPGA at board center. Reserve thermal space per datasheet (≥4 thermal vias under BGA).

• Place Power Components:
  Input filter capacitors (10 µF + 0.1 µF) within ≤3 mm of IC power pins.
  PMIC placed close to core IC to minimize power path length.

• Signal Zoning:

  • High-frequency area (≥5 GHz): near board edge, isolated from power area, enclosed by metal shielding (ground pin spacing ≤5 mm)

  • Analog area (ADC/DAC): isolated zone, ≥3 mm from digital area

  • Interface area (USB/HDMI): close to board edge, connector edge ≥5 mm from board edge

• Peripheral Component Adjustment:
  Passive components placed close to corresponding IC pins (signal path ≤5 mm), avoid cross-zone placement.

Placement Optimization and Verification

• Thermal Simulation:
  Use Flotherm; hotspot temperature ≤85 °C (otherwise add thermal vias or adjust spacing).

• Placement DRC Checks:

  • Component spacing ≥0.3 mm (power components ≥1 mm)

  • Clear polarity markings

  • BGA clearance ≥1 mm for rework

Placement Deliverables

• Dibujo de colocación de componentes

• Thermal simulation report

• Placement DRC report

Process Gate Criteria:
No thermal violations, zero critical DRC errors, manufacturer pre-review approval.

4. Laser Drilling and Via Metallization Design

Laser Drilling and Via Metallization Design

Detailed Execution Process

Drilling Scheme Design

• Define via types (blind / buried / through), generate via distribution map (diameter / depth / connected layers).

• Match laser parameters based on base material and confirm manufacturer capability.

• Via Clearance Rules:
  Via center ≥0.3 mm from pad edge, ≥0.2 mm from solder mask opening, no via overlap.

Via Metallization Process

• Plasma desmear (1000 W, 60 s) → chemical micro-etch

• Electroless copper: 28 °C, 18 mín., thickness ≥0.5 µm

• Electro Excripción: 2.5 A/dm², 75 mín., final copper thickness ≥20 µm

• Inspección de calidad: radiografía (no voids/cracks), micro-section copper coverage ≥95%

Process Gate Criteria:
No via conflicts, metallization parameters compliant, inspection passed.

5. Diseño de enrutamiento

Diseño de enrutamiento

Detailed Execution Flow (by Routing Priority)

Pre-Routing Preparation (Sub-Steps)

• Set Routing Rules:
  Trace width / espaciado (minimum 2 mil / 2 mil), impedance values (single-ended 50 Ω / differential 100 Ω), differential pair length mismatch ≤ 3 mm.

• Assign Routing Layers:
  High-speed signals → outer/inner layers adjacent to reference planes;
  Power routing → power layers;
  Low-speed signals → remaining layers.

Routing Execution (Sub-Steps)

• Power Routing:
  Calculate trace width based on current (I = 0.01 × A).
  Ejemplo: 3 A current → 1.5 mm trace width (35 μm copper).
  Power layers split to isolate different voltage domains (isolation gap ≥ 2 mm).

• High-Speed Signal Routing (Highest Priority):

  • Differential pairs: trace width = spacing (0.2 mm / 0.2 mm), parallel routing → use serpentine compensation for length mismatch (bend radius ≥ 5 × trace width).

  • Via handling: back-drill high-speed signal vias to remove stubs ≥ 1 mm, avoiding multi-layer via traversal.

  • Topology: Pítico / USB high-speed signals use Fly-by topology; branch length ≤ 30 mm.

• Analog Signal Routing:
  Routed separately, ≥3 mm from digital signals; use shielding traces (ground surrounding).

• Low-Speed Signal Routing:
  Fill remaining space, avoid parallel runs with high-speed signals (spacing ≥ 2 mm).

Ground System Design (Executed in Parallel)

• Digital Ground: continuous ground plane covering digital region.

• Analog Ground: separate plane, single-point connection to digital ground at power entry.

• High-Frequency Ground: mesh ground, grid spacing ≤ λ/20, where λ = speed of light / signal frequency.

Routing Optimization and Verification (Sub-Steps)

• Signal Integrity Simulation:
  Use Cadence Sigrity to simulate eye diagrams (eye height ≥ 0.5 V, eye width ≥ 0.5 UI).

• Routing DRC Check:
  Ensure no trace width/spacing violations, no impedance discontinuities, no ground loops.

Routing Deliverables

• Routing Layout (Gerbera / CANALLA)

• Signal Integrity Simulation Report

• Routing DRC Report

Process Gate Criteria:
Simulation results meet specifications, zero critical DRC errors, and no impedance discontinuities in high-speed signals → proceed to DFM verification.

6. DFM (Diseño para la fabricación) Verification

(Process Safeguard: Preventing Design Rework)

Detailed Execution Flow (in Inspection Sequence)

Design Self-Check (Sub-steps)

Open the DFM tools in the PCB design software (Altium DFM / Cadence DFM Check) → select inspection items (as shown in the table below) → generate a self-check report.

Manufacturer Pre-Review (Sub-steps)

• File submission:
  Gerber X2 + IPC-2581 + drill table + BOM → manufacturer issues a DFM Review Report.

• Issue correction:
  Modify the design according to manufacturer feedback
  (P.EJ., laser vias smaller than capability → adjust to manufacturer-supported minimum diameter).

Final Verification (Sub-steps)

• Secondary self-check:
  Re-run DFM tools after revisions → zero violations.

• Prototype build validation:
  Small-batch prototyping (recommended 5–10 boards) → verify solderability and signal performance.

DFM Deliverables

• DFM Self-Check Report

• Manufacturer DFM Review Report

• Revised Design Files

Process Gate Criterion:
Manufacturer approval obtained, no manufacturability-blocking issues, prototype yield ≥ 90% → proceed to surface finish selection.

7. Surface Finish Selection and Design

(Final Process Stage: Impacts Soldering Reliability & Service Life)

Detailed Execution Flow

Surface Finish Process Selection (Sub-steps)

Select based on application requirements (reference decision logic):

• Cost-sensitive: OSP (Electrónica de consumo)

• High-frequency applications: Immersion Silver / ENEPIG (estaciones base, enrutadores)

• Multiple reflow cycles: Aceptar / ENEPIG (médico, industrial)

• Harsh environments: ENEPIG (militar, aeroespacial)

Confirm manufacturer capability, Por ejemplo:

• ENIG gold thickness: 0.05–0.1 μm

• OSP thickness: 0.2–0.5 μm

Surface Finish Design Requirements (Sub-steps)

• Pad coverage:
  All soldering pads must be fully covered by surface finish; test points are recommended to be finished for probing reliability.

• Board edge handling:
  Copper-free areas along the board edge should not receive surface finish to prevent edge lifting.

Process Gate Criterion:
Surface finish matches application requirements and is manufacturable → proceed to testing and validation.

8. Testing and Validation Process

Testing and Validation Process

Detailed Execution Flow (in Test Sequence)

Prueba eléctrica (Sub-steps)

• Open/short testing:
  Flying probe tester (accuracy ±0.01 mm) → 100% cobertura (IPC-9262) → no opens or shorts.

• Impedance testing:
  TDR (Time Domain Reflectometer) → test point spacing ≤ 50 mm → deviation ≤ ±3% (high-speed signals).

• Signal integrity testing:
  Oscilloscope (bandwidth ≥ 3× signal frequency) → eye diagram meets specifications
  (eye height ≥ 0.5 V, eye width ≥ 0.5 UI).

Physical Inspection (Sub-steps)

• inspección por rayos x:
  Layer-to-layer alignment deviation ≤ ±15 μm; no blind/buried via offset.

• Micro-section analysis:
  Via wall copper thickness ≥ 20 µm; no voids or cracks.

• Surface finish inspection:
  ENIG gold thickness 0.05–0.1 μm; OSP layer free of oxidation.

Reliability Testing (Sub-steps)

• Thermal cycling test:
  −40 °C to 125 °C, 1000 cycles → no solder joint cracking.

• Damp heat aging test:
  85 °C / 85% RH, 1000 hours → insulation resistance ≥ 10¹⁰ Ω.

• Prueba de vibración:
  10–2000 Hz / 10 gramo, 6 hours → no structural damage.

Non-Conformance Handling Process

• Electrical test failure:
  Investigate routing or via metallization issues → redesign and re-verify.

• Reliability test failure:
  Optimize materials (P.EJ., high-Tg laminates) or structure (P.EJ., enhanced thermal design) → retest.

Final Deliverables

• Electrical Test Report

• Physical Inspection Report

• Reliability Test Report

• Mass Production Design Package
  (Gerbera + IPC-2581 + Proseperar + test specifications)

Process Closure Standard:
All tests passed, production files complete, and manufacturer capable of stable mass production according to documentation.