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With the trend toward miniaturization and high-density integration in electronic devices, castellated PCBs (also known as half-hole or plum-blossom-hole PCBs) have become key components in consumer electronics, industrial control, medical devices, and other fields, thanks to their core advantage of direct board-to-board connection without connectors.
The semi-cylindrical plated copper holes along the board edge not only solve the problems of bulky space occupation and high signal loss associated with traditional connectors, but also achieve breakthroughs in reliability and cost control. This article provides a comprehensive breakdown of castellated PCBs—from technical principles and manufacturing processes to design challenges and practical applications—helping engineers make accurate selections and successfully implement them in real products.
A castellated PCB is a type of circuit board in which a “semi-through conductive interface” is formed along the board edge through a combination of partial drilling, copper plating, and substrate removal. Its academic name is Castellated Holes PCB.
The core structural features include:
50%–70% of the plated copper layer is retained on the hole wall, with continuous copper coverage on the inner wall, forming a reliable conductive path;
One side of the substrate is precisely removed, exposing an arc-shaped copper surface that serves as the contact point for board-to-board soldering;
The design combines electrical conductivity (replacing connector pins) and mechanical positioning (nesting and fixation). During connection, reflow soldering is used to fuse and secure the half-hole copper surface to the pads of another PCB.
| Feature | Technical Specification | Test Standard | Industry Pain Point Addressed |
|---|---|---|---|
| Hole structure | Semi-cylindrical, located at board edge, with continuous copper plating on the hole wall | IPC-A-600G 2.4.1 | Prevents signal interruption during connection |
| Plating requirements | Hole wall copper thickness ≥ 25 μm; plating adhesion ≥ 1.5 N (no peeling in tape test) | IPC-6012 2.3.1 | Prevents plating delamination during long-term use |
| Dimensional tolerance | Hole diameter tolerance ≤ ±0.05 mm; hole position deviation ≤ ±0.03 mm | IPC-2221A 7.2 | Ensures precise board-to-board alignment and avoids cold solder joints |
| Surface finish | ENIG: nickel layer 5–8 μm, gold layer 0.05–0.1 μm; Immersion tin: tin layer 7–10 μm | IPC-4552 3.2 | Improves solderability; ENIG suitable for high-frequency applications |
| Mechanical strength | Bending strength ≥ 150 N/cm (1.6 mm board thickness); mating cycles ≥ 50 | MIL-STD-202G 211 | Suitable for vibration environments (e.g., automotive electronics) |
As electronic devices continue to shrink (such as smartwatches and Bluetooth earphones), internal space has become extremely limited. Traditional interconnection methods using connectors plus wires occupy significant space and are prone to poor contact. The half-hole PCB design effectively addresses these issues.
In conventional designs, connecting a PCB to another module requires soldering a separate connector (such as a USB connector or pin header), which typically occupies 5–10 mm of space. In contrast, half-hole PCBs integrate the connection directly into the board edge, eliminating the need for extra space—essentially integrating the connector into the PCB itself.
For example, the control module of a smart fitness band may measure only 2 cm × 3 cm, leaving no room for a traditional connector. By using a castellated PCB, the edge half-holes can be directly inserted into the main board slot, achieving reliable connection without wasting space, allowing the device to be lighter and thinner.
Similarly, in Bluetooth earphone charging interface modules, a half-hole design can reduce module thickness by 2–3 mm, perfectly matching the compact earphone enclosure.
Traditional connectors are independent components soldered onto the PCB, making them susceptible to cold solder joints or detachment. Moreover, the multiple contact points between connectors and sockets are prone to oxidation and wear over time, leading to poor contact.
In contrast, the half-holes of a castellated PCB are integrated into the board itself. The metallized holes directly contact the mating pads or slots, eliminating separate solder joints and reducing potential failure points by over 80%.
For example, industrial sensor PCBs often operate long-term in environments with vibration and dust. With traditional connectors, vibration may cause the connector to loosen or detach, interrupting data transmission. Castellated PCB edge connections eliminate the risk of loosening; even under continuous vibration, the contact between the half-holes and the slot remains stable, significantly reducing failure rates.
Traditional PCB interconnections involve three steps: PCB fabrication, connector procurement, and connector soldering. This not only incurs connector costs (a standard pin header typically costs 0.5–1 RMB per unit) but also adds extra processes and labor costs.
With castellated PCBs, the half-holes are formed during PCB manufacturing, eliminating the need to purchase connectors and perform additional soldering operations. This can save 1–2 RMB per board.
For products with annual production volumes in the millions (such as routers and smart plugs), saving just 1 RMB per board can reduce total costs by over 1 million RMB. Furthermore, simplified assembly processes can improve production efficiency by around 30%—instead of soldering connectors first and then assembling modules, manufacturers can directly insert the castellated boards, significantly shortening production time.
| Process Step | Operation Details | Key Equipment | Quality Control Points | Common Issues & Solutions |
|---|---|---|---|---|
| 1. Base Material Cutting | Select FR-4 (general applications), Rogers 4350B (high-frequency applications), or flexible PI (bendable applications). Cutting dimensional tolerance ≤ ±0.1 mm | CNC cutting machine | No burrs, no warpage of substrate | Warping: Apply pre-baking treatment (120 °C / 2 hours) |
| 2. Drilling | CNC drilling with spindle speed 30,000–50,000 rpm, feed rate 50–100 mm/min; full through-holes (φ1.0–6.0 mm) | High-precision CNC drilling machine (accuracy ±0.01 mm) | Smooth hole walls, no burrs or carbon residue | Carbon residue: Increase spindle speed; use water-soluble cutting fluid |
| 3. Electroless Copper Deposition | Degreasing (60 °C / 5 min) → Micro-etching (NaPSO₃ solution, 30 s) → Catalyzation (PdCl₂ solution, 2 min) → Electroless copper plating (45 °C, deposition rate 0.5 μm/min); final copper thickness 5–7 μm | Automatic electroless copper plating line | 100% hole wall copper coverage, no voids | Voids: Optimize copper bath concentration; extend plating time |
| 4. Pattern Transfer | Exposure (UV wavelength 365 nm, energy 80–100 mJ/cm²) → Development (Na₂CO₃ solution, 1% concentration, 30 s) → Electroplating (Copper bath: 2 A/dm², 60 min; Tin bath: 1 A/dm², 30 min); final copper thickness 25–30 μm, tin thickness 7–10 μm | Automatic electroplating line | Trace accuracy ≤ ±0.02 mm; uniform plating | Uneven plating: Adjust agitation speed; optimize rack design |
| 5. Castellated Hole Formation | Two processes: ① CNC milling: φ1.0 mm tungsten steel end mill, 40,000 rpm, feed rate 30 mm/min; milling along a position 0.5× hole diameter outside the hole center to retain half hole wall. ② Die punching: Precision die, punching pressure 5–10 MPa, positioning accuracy ±0.03 mm | CNC milling machine / Die punching machine | No burrs on half-hole wall; no copper delamination | Burrs: Add post-milling deburring (nylon brushing + chemical deburring) |
| 6. Etching & Post-Processing | Etching (CuCl₂ solution, etch rate 2 μm/min) → Solder mask (silkscreen printing, thickness 10–20 μm) → Legend printing → Inspection (AOI + X-ray) | Automatic etching line, AOI inspection equipment | Accurate solder mask openings (deviation ≤ ±0.03 mm); no shorts/opens | Solder mask misalignment: Optimize screen alignment; improve exposure accuracy |
| Process Dimension | CNC Milling | Die Punching | Practical Selection Recommendation |
|---|---|---|---|
| Precision | Hole diameter tolerance ±0.05 mm; hole wall roughness Ra ≤ 0.8 μm | Hole diameter tolerance ±0.1 mm; hole wall roughness Ra ≤ 1.2 μm | CNC preferred for high-precision applications such as medical and military |
| Efficiency | Single-sided board processing time: 30 s / panel (10 castellated holes); changeover time 5 min | Single-sided board processing time: 1 s / panel; changeover time 30 min | Die punching for mass production (>100k pcs); CNC for small batches (<10k pcs) |
| Tooling Cost | No mold cost; tool wear cost approx. 0.1 RMB / board | Mold development cost USD 5,000–15,000 per set; mold life approx. 1 million cycles | CNC is more cost-effective for orders <50k pcs |
| Applicable Hole Diameter | Minimum hole diameter 0.4 mm (board thickness ≤ 1.0 mm) | Minimum hole diameter 0.6 mm | Micro-hole designs (<0.6 mm) require CNC |
| Edge Quality | No compression damage; excellent copper integrity | Minor compression marks possible (probability <3%) | CNC recommended for high-frequency, signal-sensitive applications |
| Typical Customers | Medical device manufacturers (e.g., Mindray), defense industry companies | Consumer electronics manufacturers (e.g., Xiaomi, OPPO) | Decide based on product positioning and order volume |
The core advantage of castellated PCBs lies in miniaturized interconnection, making them especially suitable for devices with limited space and high requirements for connection reliability. Typical applications include:
Wireless modules and Gigabit Ethernet interface modules inside routers are widely implemented using castellated PCBs.
For example, a router’s 5G wireless module typically measures only 3 cm × 4 cm. By inserting the castellated PCB directly into the mainboard slot, space is saved while ensuring stable transmission of high-speed network signals. If traditional connectors were used, signal attenuation could occur during transmission, negatively affecting network speed.
These devices feature extremely compact form factors (a smartwatch mainboard typically has an area of only about 5 cm²), leaving no room for conventional connectors. Castellated PCBs are an ideal solution.
For instance, the heart-rate sensor module of a smartwatch can be connected to the mainboard via castellated holes, allowing the module thickness to be controlled within 1 mm, perfectly fitting into the slim device enclosure. Moreover, castellated connections are highly reliable and will not suffer from poor contact due to wrist movement.
Industrial sensors are required to operate for long periods in harsh environments such as vibration, high temperature, and dust, and are often installed in narrow mechanical spaces.
The edge-connection method of castellated PCBs eliminates the risk of loosening, ensuring stable sensor data transmission. At the same time, the absence of additional connectors reduces gaps through which dust and moisture could enter, significantly improving the sensor’s water and dust resistance.
For example, in smartphone wireless charging pads, the internal control module often uses a castellated PCB, with the half-holes directly connected to the charging coil. This design reduces overall module thickness (down to below 0.5 mm) while ensuring stable charging current transmission.
Similarly, in USB Bluetooth adapters, the internal Bluetooth module is connected to the USB interface board via castellated holes, enabling the adapter to be as compact as a USB flash drive.
| Comparison Dimension | Castellated PCB | Standard Through-Hole PCB | Blind/Buried Via PCB | Selection Guidance |
|---|---|---|---|---|
| Hole Location | Board edge only | Anywhere on board | Inner layers / surface layers (non-through) | Castellated: board-to-board connection; Through-hole: interlayer conduction; Blind/Buried: high-density internal routing |
| Core Function | Board-to-board connection + mechanical fixation | Electrical interlayer connection | Internal signal interconnection (saves surface space) | — |
| Manufacturing Process | Drilling → Plating → Milling / Punching | Drilling → Plating → Etching | Laser drilling → Plating → Lamination | Castellated process is the most complex and costly |
| Cost Level | 20–30% higher than standard through-hole | Baseline (100%) | 50–80% higher than standard through-hole | Cost-sensitive designs choose through-hole; high-density designs choose blind/buried |
| Precision Requirement | Strict (±0.05 mm) | Moderate (±0.1 mm) | Very strict (±0.02 mm) | Medical and military prefer castellated / blind vias |
| Signal Performance | Low high-frequency loss (up to 5 GHz) | Moderate high-frequency loss | Lowest high-frequency loss (10 GHz+) | 5G and radar prefer blind vias; consumer electronics prefer castellated |
| Evaluation Item | Qualified Standard | Excellent Standard | Verification Method |
|---|---|---|---|
| Machining accuracy | Hole tolerance ±0.05 mm; position deviation ±0.03 mm | Hole tolerance ±0.03 mm; position deviation ±0.02 mm | CNC equipment model list (e.g., Mitsubishi MV2400), inspection reports |
| Plating control | Copper thickness ≥25 μm; adhesion ≥1.5 N | Copper thickness 25–30 μm; adhesion ≥2.0 N | Plating thickness reports (XRF), tape test videos |
| High-frequency capability | Dielectric constant deviation ≤±5% (Rogers materials) | Dielectric constant deviation ≤±3% | Impedance test reports (TDR) |
Certifications: ISO 9001 (basic), ISO 13485 (medical devices), AS9100 (aerospace);
Inspection Equipment: AOI automatic optical inspection (100% coverage), X-ray inspection (hole wall void detection), impedance testers (for high-frequency applications);
Quality Control Flow: Incoming inspection (IQC) → In-process inspection (IPQC) → Final inspection (FQC) → Outgoing inspection (OQC), with defect rate controlled at PPM < 50.
Pre-sales: DFM design consultation (hole layout, material selection), response time ≤ 2 hours;
In-production: Real-time production progress updates (twice-weekly reports), abnormal issue resolution ≤ 24 hours;
After-sales: 3-month warranty (free repair for non-human damage), lifetime technical support.
Production equipment: Availability of high-precision CNC milling machines (e.g., DMG MORI), automatic plating lines, AOI inspection systems;
Process documentation: Complete castellated PCB SOPs and quality control plans (QCP);
Customer cases: Experience with high-end industries such as medical, military, and automotive electronics (e.g., Huawei, Mindray);
Production capacity: Monthly output ≥ 500,000 pcs; sample lead time ≤ 3 days; mass production lead time ≤ 7 days.
Leadsintec
Technical strengths: 20 Mitsubishi CNC milling machines; machining accuracy ±0.03 mm; high-frequency castellated PCB impedance control within ±3%;
Quality certifications: ISO 9001, ISO 13485, AS9100; medical-grade products passed biocompatibility testing;
Service assurance: Free DFM optimization, 3-day sample delivery, 7-day mass production delivery, lifetime technical support;
Customer cases: Castellated PCBs for Mindray glucose meters and Huawei 5G modules, with defect rates controlled at PPM < 30.
As a core technology enabling miniaturization and high-density integration, castellated (half-hole) PCBs have proven their technical advantages across consumer electronics, industrial control, and medical device applications.
By thoroughly understanding their definitions, characteristics, manufacturing processes, and design specifications—and by selecting appropriate fabrication methods and suppliers based on real application scenarios—manufacturers can significantly improve product reliability, reduce costs, and shorten development cycles.
If you require customized castellated PCB solutions (for high-frequency, medical, or military applications), or need DFM optimization and cost evaluation, you are welcome to contact Leadsintec for free technical consultation and sample testing.
In the electronics manufacturing industry, “design is manufacturing” is no longer just a slogan, but a consensus validated through numerous mass-production projects.
Based on our involvement in multiple consumer electronics and industrial control products, PCB Design for Manufacturability (DFM) is often the key factor that determines whether mass production proceeds smoothly.
From an engineering perspective, PCB designs that lack systematic DFM verification show a significantly higher probability of placement defects, rework, or even redesign during early mass production. According to statistical experience from multiple contract manufacturers, designs without sufficient DFM optimization often achieve a first-run production yield of below 80%. In contrast, projects that incorporate IPC standards and manufacturing capability checks at the design stage can consistently improve yields to the 95%–98% range.
This article combines the latest IPC standards, SMT/THT hybrid process requirements, and common issues observed in real mass-production projects to systematically break down the core elements of PCB assembly DFM. The goal is to help engineers minimize manufacturing risks during the design phase and truly achieve “design once, mass-produce smoothly.”
The foundation of DFM design lies in following unified industry standards to avoid rework caused by misalignment between design intent and manufacturing processes.
IPC-2581 Revision C
Released in 2020, this latest standard integrates complete PCB manufacturing, assembly, and test data into a single XML file, including stack-up information, impedance control, and differential pair definitions. It replaces traditional fragmented Gerber files and improves DFM analysis automation efficiency by approximately 60%.
IPC-2221
Defines fundamental process parameters such as trace width, spacing, and hole size. For example, low-voltage circuits (≤50V) require a minimum spacing of ≥4 mil (0.1 mm), while high-voltage circuits (>50V) must calculate clearance using the formula:
Clearance = 0.6 + 500 × Vpeak (mm).
IPC-7351
Standardizes component land pattern and pad design to ensure placement accuracy and solder joint reliability.
Priority should be given to standard components (such as 0402/0603 resistors and capacitors), avoiding niche or customized parts. Customized components not only have longer procurement lead times (typically >4 weeks) but can also increase assembly costs by more than 30%.
Simplify PCB structures by minimizing the use of special processes such as blind/buried vias and stepped slots. For conventional HDI boards, a combination of laser drilling + mechanical drilling can effectively reduce manufacturing costs.
Improper layout is a primary cause of SMT placement deviation and solder bridging, and the following rules should be strictly observed:
Component spacing guidelines:
Spacing between identical components ≥3–4 mil (standard process) or ≥2 mil (high-precision HDI), to avoid collisions with pick-and-place nozzles;
Spacing between irregular components (such as connectors and heat sinks) and surrounding components ≥1 mm, allowing sufficient tool access during assembly;
Follow the “3W rule”: high-speed signal spacing ≥3× trace width; differential pair spacing ≈ trace width; spacing between differential pairs ≥3W to reduce crosstalk.
Orientation consistency:
Polarized components (capacitors, diodes) should have a uniform orientation to avoid polarity confusion during manual soldering;
IC pin orientation should align with pick-and-place feeder direction to reduce nozzle adjustments and improve placement efficiency.
When a PCB includes both surface-mount (SMT) and through-hole (THT) components, compatibility between the two processes must be considered:
THT components should be grouped near PCB edges or in designated areas to avoid blocking SMT pads and causing wave-solder “shadow effects”;
Spacing between through-hole pins and SMT components should be ≥2 mm to prevent damage to already soldered SMT joints during insertion;
For mixed reflow + wave soldering processes, THT components should use wave-solder-compatible packages to prevent lead oxidation caused by high temperatures.
High-power components (such as DC-DC converters and LED drivers) should be placed near PCB edges or thermal copper areas. The copper area should be at least 2× the component package area, and thermal via arrays may be required (via diameter 0.3 mm, pitch 1 mm);
In vibration environments (automotive, industrial equipment), critical components (such as CPUs and power modules) should preferably use THT packages, whose solder joints offer over 5× higher vibration resistance than SMT;
Reserve a copper-free area ≥0.025 inches (0.635 mm) along PCB edges to prevent cracking during depanelization.
Pad dimension deviations are a major cause of cold solder joints and tombstoning, and must closely match component packages:
SMT component pads:
Length = lead length + 0.2 mm;
Width = lead width ±0.1 mm.
For example, a 0603 resistor (1.6 mm × 0.8 mm) corresponds to a pad size of 1.8 mm × 0.7 mm.
QFP/BGA pads:
BGA pad diameter = ball diameter × 0.6–0.7;
Spacing between adjacent pads ≥ ball diameter × 1.2 to prevent bridging.
Thermal pad design:
For high-power components (e.g., QFN packages), the exposed thermal pad should use solder mask openings and include 4–6 thermal vias (0.3 mm diameter) to prevent heat accumulation and cold solder joints.
Drilling rules:
Aspect ratio (hole depth / hole diameter) ≤6:1 for standard processes and ≤10:1 for HDI processes; exceeding this requires stepped holes or back drilling;
Via diameter ≥0.3 mm; component lead hole diameter = lead diameter + 0.1–0.2 mm to ensure smooth insertion;
Avoid edge holes: drilling center must be ≥1 mm from the PCB edge to prevent board cracking.
Trace width must satisfy both current capacity and process limits:
Calculated according to IPC-2152:
I = k · ΔT^0.44 · A^0.725
(k = 0.048 for outer layers, k = 0.024 for inner layers).
For example, with 1 oz copper and a 10°C temperature rise, a 50 mil trace can carry approximately 2.5 A.
Power and ground nets should preferably use copper pours instead of thin traces, with copper thickness ≥2 oz to reduce ground impedance and thermal stress;
Minimum trace width: ≥3–4 mil for standard processes and ≥2 mil for HDI processes to avoid etching residues and short circuits.
Impedance control:
For a 50 Ω single-ended trace on FR-4, outer-layer microstrip width ≈8 mil (h = 5 mil), inner-layer stripline width ≈5 mil (h = 4 mil);
Differential pair routing:
Length mismatch ≤5 mil; avoid impedance discontinuities and via crossings between pairs;
Avoid right-angle routing:
Use 45° bends or arcs (radius ≥3× trace width) to reduce signal reflection.
The Bill of Materials (BOM) is the core reference for manufacturing execution and must meet the requirements of “zero ambiguity and complete information.”
Mandatory fields:
Manufacturer name and part number, reference designators (sorted A–Z), quantity, package type, alternate part numbers, MSL level (Moisture Sensitivity Level), and critical component flag (non-substitutable);
Error prevention:
Remove duplicate reference designators, ensure consistency between quantities and reference designators, and clearly mark DNP (Do Not Populate) components separately;
Format standardization:
Use Excel format and separate tabs for “PCB main components,” “auxiliary materials,” and “tools,” enabling manufacturers to quickly import data into production systems.
Provide 2D assembly drawings indicating key component locations, polarity orientation, and torque requirements (e.g., screw tightening torque);
Clearly specify process requirements, such as “reflow soldering temperature profile (peak 260 °C, soak time 10 s)” and “wave soldering conveyor speed 1.2 m/min”;
Include IPC-2581 data files to allow manufacturers to quickly import data into DFM analysis tools and automatically verify design compliance.
HuaQiu DFM:
One of the first free domestic tools, capable of one-click analysis of more than 23 design risk items (including pad deviation, hole size anomalies, and spacing conflicts). It supports one-click export of Gerber/BOM/placement files, with reports viewable on mobile devices;
JiePei DFM:
Built-in SMT process checking rules, capable of real-time PCB manufacturing cost estimation and surcharge warnings (such as gold fingers and special substrates);
SolidWorks DFMXpress:
A free plugin integrated into SolidWorks, focusing on DFM checks for machined parts (such as hole aspect ratio and thin-wall risks).
Geometric DFMPro:
Supports multiple CAD platforms including SolidWorks, CATIA, and NX, covering injection molding, sheet metal, and additive manufacturing processes. It allows customization of enterprise-specific rule libraries and generates detailed analysis reports;
aPriori:
A high-end manufacturing simulation platform that performs DFM checks while accurately estimating manufacturing costs (materials + processing + labor) and carbon footprint, suitable for large-scale mass production projects;
VayoPro-DFM Expert:
Focused on PCBA applications, supporting thousands of inspection rules, 3D assembly simulation, and component collision risk detection.
| Application Scenario | Recommended Tools | Core Advantages |
|---|---|---|
| Startups / Individuals | HuaQiu DFM + JiePei DFM | Free, easy to use, covers core PCB/SMT checks |
| Multi-CAD environments / Complex processes | Geometric DFMPro | Cross-platform, customizable, multi-process support |
| Cost-sensitive mass production projects | aPriori | Integrated cost estimation and DFM analysis |
Design phase:
Perform automated DFM checks after completing each module (such as layout or routing), focusing on spacing, pad design, and hole size;
Prototype validation:
Produce 3–5 prototype boards and conduct actual placement tests, recording placement yield and solder defect locations to drive design optimization;
Pre-production review:
Hold DFM review meetings with PCB manufacturers and SMT assembly houses to confirm alignment with process capabilities (e.g., minimum trace width and drilling accuracy).
Share IPC-2581 data files in advance, allowing manufacturers to perform DFM analysis early and provide optimization feedback (typically requiring 3–5 working days);
Clearly communicate special requirements, such as “BGA requires X-ray inspection” or “power modules require separate burn-in testing,” to avoid misunderstandings during mass production.
The WiFi module PCB of BILIAN ELECTRONIC exhibited the following issues in its initial design:
BGA pad spacing of only 0.8 mm (below the IPC-7351 recommended 1.0 mm);
Power trace width of 10 mil, with current capacity below 1 A, insufficient for peak module current;
Use of a niche connector in the BOM, resulting in a 6-week procurement lead time.
Optimization measures:
Increased BGA pad spacing to 1.2 mm, with pad diameter designed at 0.6× ball diameter;
Widened power traces to 50 mil (1 oz copper, current capacity 2.5 A) and added ground copper pours;
Replaced the connector with a standard Micro USB connector available from stock.
Optimization results:
Placement yield increased from 82% to 99.2%;
Mass production cycle shortened from 8 weeks to 4 weeks;
Manufacturing cost per PCB reduced by 28%.
The essence of PCB assembly DFM lies in designers optimizing designs from the manufacturing perspective. From standards compliance and layout rationality to process compatibility and information transfer, every stage must balance performance requirements with manufacturability.
With the adoption of intelligent standards such as IPC-2581 and the application of AI-driven DFM tools, DFM has evolved from an experience-based approach to a data-driven methodology. Engineers are strongly encouraged to establish a DFM checklist early in the design phase and combine the rules and tools outlined in this article to eliminate issues at the design stage—ultimately achieving simultaneous optimization of product yield, cost, and time-to-market.
If you encounter specific DFM challenges (such as hybrid-process layout or impedance control calculations), feel free to leave a comment. We will provide targeted solutions.
HDI PCB (High Density Interconnect printed circuit board) is a key enabling technology for achieving miniaturization, high performance, and high reliability in modern high-end electronic products. As chip I/O counts continue to increase and signal speeds keep rising, traditional PCBs are gradually becoming insufficient in terms of routing density, signal integrity, and package compatibility. HDI PCBs, through the use of microvias, blind vias, buried vias, and multi-step lamination structures, provide a more optimized solution for complex circuit designs.
The design of HDI PCBs is not simply a matter of “reducing trace width and increasing layer count,” but rather a systematic engineering process that spans system architecture, electrical performance, manufacturing processes, and cost control. This article provides a step-by-step, detailed, and engineering-oriented explanation of the HDI PCB design process, making it suitable for use as a technical blog, corporate website technical documentation, or in-depth SEO content.
HDI PCB refers to a multilayer printed circuit board that achieves high-density interconnection by using laser-drilled microvias and employing blind vias, buried vias, and multiple lamination processes. Its fundamental objective is to:
achieve more component interconnections, shorter signal paths, and more stable electrical performance within a limited PCB area.
Smartphones and tablet computers
Wearable devices
Automotive electronics (ADAS, BMS, intelligent cockpit systems)
Medical electronics and high-reliability equipment
Communication and high-speed computing equipment
| Item | Traditional PCB | HDI PCB |
|---|---|---|
| Interconnection method | Mainly through-holes | Microvias, blind vias, buried vias |
| Routing density | Medium to low | Extremely high |
| Signal path length | Longer | Shorter |
| Supported packages | QFP, low I/O BGA | High I/O BGA, CSP, Flip-Chip |
Convert abstract requirements into actionable design specifications and confirm manufacturing feasibility.
Confirmation with Product Team:
Application scenarios (consumer electronics / medical / industrial), operating environment (temperature / humidity / vibration), product lifecycle (≥5 years requires enhanced reliability)
Confirmation with Hardware Engineers:
Core IC models (e.g., BGA package parameters), power architecture (voltage levels / current requirements), signal types (high-speed / analog / digital)
Preliminary Communication with PCB Manufacturer:
Confirm manufacturing limits (minimum laser via diameter / maximum layer count / impedance control capability)
| Core Document Module | Mandatory Content | Example Specification |
|---|---|---|
| Electrical Parameters | Signal frequency, impedance requirements, current thresholds | High-speed signal: PCIe 4.0 (16 Gbps), single-ended 50 Ω ±3% |
| Physical Parameters | Board size, thickness, weight limits | Board size: 120 × 80 mm, thickness: 1.6 mm (±0.1 mm) |
| Reliability Requirements | Temperature/humidity range, vibration rating | Operating temperature: –40 °C to 85 °C, vibration: 10–2000 Hz / 10 g |
| Manufacturing Constraints | Manufacturer process limits, cost budget | Cost limit: 150 RMB / board, laser via ≥0.1 mm supported |
Design Software Setup:
Install corresponding plugins (Altium → HDI Toolkit; Cadence → Microvia Optimizer), import manufacturer process libraries (IPC-2226A standard templates)
Reference Material Collection:
Core IC datasheets (focus on package pinout and power requirements), manufacturer process specifications (laser drilling parameters / lamination process), industry standards (IPC-6012E)
Process Gate Decision:
Proceed to the next step only after SOR document approval and manufacturer process feasibility confirmation (manufacturer must issue a Process Compatibility Confirmation Letter).
Stack-Up Design
Define layer structure, blind/buried via distribution, and impedance control strategy to enable subsequent routing.
Signal Layer Estimation:
Calculate required signal layers based on critical signals (high-speed / differential).
Follow the principle: one signal layer corresponds to one reference layer.
Example: 8 PCIe 4.0 differential pairs → 4 signal layers + 4 reference layers = 8 layers
Power/Ground Layer Allocation:
Divide by voltage domains (e.g., 3.3 V / 1.8 V / core voltage).
Each major voltage domain requires at least one power layer and one adjacent ground layer.
Blind/Buried Via Layer Matching:
If blind vias are required for “Top → L2” and “L7 → Bottom”, and buried vias for “L3 → L6”, the stack-up must be:
Top (S1) – L2 (S2) – L3 (P1) – L4 (G1) – L5 (G2) – L6 (P2) – L7 (S3) – Bottom (S4)
Layer Thickness Allocation:
Standard combination: signal layer 0.07 mm + dielectric 0.1 mm + power layer 0.1 mm
Example total thickness 1.6 mm:
0.07 × 4 + 0.1 × 3 + 0.1 × 1 = 1.6 mm
Impedance Simulation and Validation:
Use Ansys SIwave, input layer thickness and Dk values, simulate single-ended and differential impedance.
Adjust dielectric thickness if impedance deviates (e.g., increase dielectric thickness if impedance is too low).
Blind/Buried Via Path Planning:
Draw via connection diagrams (e.g., S1→S2 blind via, S3→S4 blind via, L3→L6 buried via) to avoid via overlap.
Stack-up structure drawing (layer thickness / materials / via types)
Impedance simulation report
Blind/buried via distribution table
Process Gate Criteria:
Impedance error ≤ ±3%, blind/buried via aspect ratio ≤ 0.75:1, layer-to-layer alignment meets manufacturer requirements (within ±25 μm).
Component Selection and Placement Design
Package Priority:
Prefer 0201 / 01005 packages (confirm SMT capability); core ICs prioritize BGA/CSP packages to reduce footprint.
Material Compatibility Check:
Confirm pin pitch (≥0.4 mm for routing feasibility), power dissipation (≤2 W per component; higher requires thermal design).
Fix Core Components:
Place CPU/GPU/FPGA at board center. Reserve thermal space per datasheet (≥4 thermal vias under BGA).
Place Power Components:
Input filter capacitors (10 µF + 0.1 µF) within ≤3 mm of IC power pins.
PMIC placed close to core IC to minimize power path length.
Signal Zoning:
High-frequency area (≥5 GHz): near board edge, isolated from power area, enclosed by metal shielding (ground pin spacing ≤5 mm)
Analog area (ADC/DAC): isolated zone, ≥3 mm from digital area
Interface area (USB/HDMI): close to board edge, connector edge ≥5 mm from board edge
Peripheral Component Adjustment:
Passive components placed close to corresponding IC pins (signal path ≤5 mm), avoid cross-zone placement.
Thermal Simulation:
Use Flotherm; hotspot temperature ≤85 °C (otherwise add thermal vias or adjust spacing).
Placement DRC Checks:
Component spacing ≥0.3 mm (power components ≥1 mm)
Clear polarity markings
BGA clearance ≥1 mm for rework
Component placement drawing
Thermal simulation report
Placement DRC report
Process Gate Criteria:
No thermal violations, zero critical DRC errors, manufacturer pre-review approval.
Laser Drilling and Via Metallization Design
Define via types (blind / buried / through), generate via distribution map (diameter / depth / connected layers).
Match laser parameters based on base material and confirm manufacturer capability.
| Via Type | Diameter (µm) | Layer Connection | Laser Parameters (FR-4) | Drilling Sequence |
|---|---|---|---|---|
| Top blind via | 80–100 | S1 → L2 | 35 W, 70 kHz | Blind → buried → through |
| Bottom blind via | 80–100 | L7 → S4 | 35 W, 70 kHz | |
| Buried via | 150–200 | L3 → L6 | 40 W, 80 kHz | |
| Thermal through via | 300–500 | S1 → S4 | 50 W, 60 kHz |
Via Clearance Rules:
Via center ≥0.3 mm from pad edge, ≥0.2 mm from solder mask opening, no via overlap.
Plasma desmear (1000 W, 60 s) → chemical micro-etch
Electroless copper: 28 °C, 18 min, thickness ≥0.5 µm
Electroplating: 2.5 A/dm², 75 min, final copper thickness ≥20 µm
Quality inspection: X-ray (no voids/cracks), micro-section copper coverage ≥95%
Process Gate Criteria:
No via conflicts, metallization parameters compliant, inspection passed.
Routing Design
Set Routing Rules:
Trace width / spacing (minimum 2 mil / 2 mil), impedance values (single-ended 50 Ω / differential 100 Ω), differential pair length mismatch ≤ 3 mm.
Assign Routing Layers:
High-speed signals → outer/inner layers adjacent to reference planes;
Power routing → power layers;
Low-speed signals → remaining layers.
Power Routing:
Calculate trace width based on current (I = 0.01 × A).
Example: 3 A current → 1.5 mm trace width (35 μm copper).
Power layers split to isolate different voltage domains (isolation gap ≥ 2 mm).
High-Speed Signal Routing (Highest Priority):
Differential pairs: trace width = spacing (0.2 mm / 0.2 mm), parallel routing → use serpentine compensation for length mismatch (bend radius ≥ 5 × trace width).
Via handling: back-drill high-speed signal vias to remove stubs ≥ 1 mm, avoiding multi-layer via traversal.
Topology: PCIe / USB high-speed signals use Fly-by topology; branch length ≤ 30 mm.
Analog Signal Routing:
Routed separately, ≥3 mm from digital signals; use shielding traces (ground surrounding).
Low-Speed Signal Routing:
Fill remaining space, avoid parallel runs with high-speed signals (spacing ≥ 2 mm).
Digital Ground: continuous ground plane covering digital region.
Analog Ground: separate plane, single-point connection to digital ground at power entry.
High-Frequency Ground: mesh ground, grid spacing ≤ λ/20, where λ = speed of light / signal frequency.
Signal Integrity Simulation:
Use Cadence Sigrity to simulate eye diagrams (eye height ≥ 0.5 V, eye width ≥ 0.5 UI).
Routing DRC Check:
Ensure no trace width/spacing violations, no impedance discontinuities, no ground loops.
Routing Layout (Gerber / CAD)
Signal Integrity Simulation Report
Routing DRC Report
Process Gate Criteria:
Simulation results meet specifications, zero critical DRC errors, and no impedance discontinuities in high-speed signals → proceed to DFM verification.
(Process Safeguard: Preventing Design Rework)
Open the DFM tools in the PCB design software (Altium DFM / Cadence DFM Check) → select inspection items (as shown in the table below) → generate a self-check report.
| Inspection Category | Specific Check Items | Acceptance Criteria | Corrective Actions |
|---|---|---|---|
| Pad Design | Pad size, spacing, solder mask opening | Pad ≥ 0.25 mm; solder mask opening = pad + 0.2 mm | Adjust pad size / solder mask opening |
| Via Design | Via spacing, hole size, solder mask coverage | Via spacing ≥ 0.3 mm; solder mask coverage on via edge ≥ 0.1 mm | Adjust via location / hole size |
| Silkscreen Design | Line width, distance to pads | Line width ≥ 0.15 mm; distance to pad ≥ 0.2 mm | Move silkscreen / increase line width |
| Board Edge Design | Copper keep-out, tooling hole position | Copper keep-out ≥ 0.5 mm; tooling hole ≥ 5 mm from board edge | Increase keep-out area / adjust tooling holes |
File submission:
Gerber X2 + IPC-2581 + drill table + BOM → manufacturer issues a DFM Review Report.
Issue correction:
Modify the design according to manufacturer feedback
(e.g., laser vias smaller than capability → adjust to manufacturer-supported minimum diameter).
Secondary self-check:
Re-run DFM tools after revisions → zero violations.
Prototype build validation:
Small-batch prototyping (recommended 5–10 boards) → verify solderability and signal performance.
DFM Self-Check Report
Manufacturer DFM Review Report
Revised Design Files
Process Gate Criterion:
Manufacturer approval obtained, no manufacturability-blocking issues, prototype yield ≥ 90% → proceed to surface finish selection.
(Final Process Stage: Impacts Soldering Reliability & Service Life)
Select based on application requirements (reference decision logic):
Cost-sensitive: OSP (consumer electronics)
High-frequency applications: Immersion Silver / ENEPIG (base stations, routers)
Multiple reflow cycles: ENIG / ENEPIG (medical, industrial)
Harsh environments: ENEPIG (military, aerospace)
Confirm manufacturer capability, for example:
ENIG gold thickness: 0.05–0.1 μm
OSP thickness: 0.2–0.5 μm
Pad coverage:
All soldering pads must be fully covered by surface finish; test points are recommended to be finished for probing reliability.
Board edge handling:
Copper-free areas along the board edge should not receive surface finish to prevent edge lifting.
Process Gate Criterion:
Surface finish matches application requirements and is manufacturable → proceed to testing and validation.
Testing and Validation Process
Open/short testing:
Flying probe tester (accuracy ±0.01 mm) → 100% coverage (IPC-9262) → no opens or shorts.
Impedance testing:
TDR (Time Domain Reflectometer) → test point spacing ≤ 50 mm → deviation ≤ ±3% (high-speed signals).
Signal integrity testing:
Oscilloscope (bandwidth ≥ 3× signal frequency) → eye diagram meets specifications
(eye height ≥ 0.5 V, eye width ≥ 0.5 UI).
X-ray inspection:
Layer-to-layer alignment deviation ≤ ±15 μm; no blind/buried via offset.
Micro-section analysis:
Via wall copper thickness ≥ 20 μm; no voids or cracks.
Surface finish inspection:
ENIG gold thickness 0.05–0.1 μm; OSP layer free of oxidation.
Thermal cycling test:
−40 °C to 125 °C, 1000 cycles → no solder joint cracking.
Damp heat aging test:
85 °C / 85% RH, 1000 hours → insulation resistance ≥ 10¹⁰ Ω.
Vibration test:
10–2000 Hz / 10 g, 6 hours → no structural damage.
Electrical test failure:
Investigate routing or via metallization issues → redesign and re-verify.
Reliability test failure:
Optimize materials (e.g., high-Tg laminates) or structure (e.g., enhanced thermal design) → retest.
Electrical Test Report
Physical Inspection Report
Reliability Test Report
Mass Production Design Package
(Gerber + IPC-2581 + BOM + test specifications)
Process Closure Standard:
All tests passed, production files complete, and manufacturer capable of stable mass production according to documentation.
| Process Stage | Core Deliverables | Gate Criteria | Common Issue Handling Methods |
|---|---|---|---|
| Requirements Analysis | SOR (Statement of Requirements), Manufacturer Process Capability Confirmation | Requirements clearly defined with no ambiguity; manufacturing feasibility confirmed | Vague requirements → organize a three-party review (product / hardware / manufacturer) |
| Stack-Up Design | Stack-up structure diagram, impedance simulation report | Impedance deviation ≤ ±3%; blind/buried vias compliant | Impedance out of spec → adjust dielectric thickness or Dk values |
| Component Placement | Placement layout, thermal simulation report | Thermal simulation ≤ 85 °C; zero critical DRC violations | Hot spots exceed limit → add thermal vias or reposition components |
| Drilling Design | Via distribution diagram, via quality inspection report | No voids in via walls; hole diameters meet specifications | Via conflicts → replan blind/buried via routing paths |
| Routing Design | Routing layout, signal integrity (SI) simulation report | Eye diagram compliant; zero critical DRC violations | Excessive signal loss → optimize routing or switch to low-Df materials |
| DFM Verification | DFM review report, corrective design files | Manufacturer approval obtained; zero manufacturing risks | Manufacturing violations → revise design per manufacturer feedback |
| Surface Finish Selection | Surface finish specification document | Process matches application requirements | Unsupported process → switch to alternative surface finish |
| Testing & Validation | Full test reports, mass production file package | All tests passed; documentation complete |
Test failure → identify root cause (design / process) → corrective action and re-test |
HDI PCB design is a highly integrated engineering activity that involves system architecture, electrical performance, manufacturing processes, and cost control. Through a scientific design workflow, well-planned HDI structure selection, and close collaboration with PCB manufacturers, designers can significantly improve design success rates and overall product reliability.
From a technical content marketing perspective, systematic, in-depth, and engineering-oriented HDI PCB design process content is more likely to gain long-term recognition from both search engines and professional audiences.
As the global hub of electronic manufacturing, Shenzhen boasts a dense cluster of low-volume PCB manufacturers that cater to the needs of R&D teams, startups, and small-to-medium enterprises (SMEs). This guide explores the core advantages, technical capabilities, and selection criteria of Shenzhen’s low-volume PCB manufacturers, helping you find the ideal partner for your project.
Shenzhen’s PCB industry benefits from a mature ecosystem covering raw materials, electronic components, and auxiliary services. Concentrated in industrial zones such as Shajing, Fuyong, and Songgang, manufacturers have access to over 500 local suppliers, enabling:
24-hour procurement of key materials (FR-4, high-frequency substrates, aluminum substrates)
A 30% reduction in lead time for custom components compared with other regions
Cost optimization through shared supply chains (e.g., component splitting for small orders)
Traditional PCB manufacturers prioritize mass production, resulting in long lead times (15–20 days) for small orders. Shenzhen’s specialized low-volume PCB factories overcome this challenge through:
Flexible production lines supporting orders from 1 to 1,000 units
Rapid line changeover (60 minutes versus the industry average of 3–4 hours)
Emergency delivery options (48–72 hours for prototype orders)
Digital production management with real-time order tracking
Manufacturers in Shenzhen invest heavily in advanced equipment and R&D, supporting cutting-edge technical requirements, including:
Multi-layer PCB capabilities (2–64 layers for prototypes, 2–58 layers for low-volume production)
High-precision manufacturing (minimum trace width/spacing of 3/3 mil, laser-drilled holes down to 0.1 mm)
Special processes: HDI boards, resin-filled vias, thick copper boards (up to 6 oz) for power electronics
Compliance with international standards (ISO9001, IATF16949, RoHS, REACH)
Leading manufacturers provide end-to-end services beyond PCB fabrication, including:
DFM (Design for Manufacturability) review within 24 hours to optimize designs
One-stop PCBA services (SMT assembly, DIP insertion, functional testing)
Personalized technical consulting (material selection, cost optimization)
Global shipping to over 180 countries with customs clearance support
| Process Parameter | Industry Standard Range | Capabilities of Leading Shenzhen Manufacturers |
|---|---|---|
| Layer count | 2–12 layers | 2–64 layers (prototypes) / 2–58 layers (production) |
| Minimum trace/spacing | 5/5 mil | 3/3 mil (multilayer) / 4/4 mil (production) |
| Board thickness | 0.8–2.0 mm | 0.2–17.5 mm (prototypes) / 0.6–10 mm (production) |
| Minimum hole size | 0.3 mm (mechanical drill) | 0.1 mm (laser drill) / 0.2 mm (mechanical, production) |
| Surface finish | HASL, ENIG | HASL, ENIG, OSP, ENEPIG, and other customized options |
| Lead time | 7–15 days | Emergency: 48–72 hours / Standard: 3–7 days |
| Yield rate | 95%+ | 99.7%+ (full-process AOI inspection) |
Data source: publicly available information from leading manufacturers such as Huaqiu PCB, JLCPCB, and Xiaoming Prototype.
Certifications: ISO9001 (quality) and RoHS (environmental compliance) are essential; ISO13485 is required for medical electronics, and IATF16949 for automotive electronics
Production equipment: Confirm the availability of LDI exposure machines, AOI inspection systems, laser drilling machines, and other high-precision equipment
Testing capabilities: Check whether value-added services such as ICT testing, functional testing (FCT), and impedance testing are provided
Minimum order quantity: Whether ultra-low-volume orders of 1–10 boards are supported
Line changeover efficiency: Whether line changeover and setup time is ≤2 hours (60 minutes is considered industry best practice)
Urgent order response: Ability to ship within 72 hours for R&D and prototype needs
Quotation transparency: Whether detailed cost breakdowns are provided (materials, processes, testing, logistics)
Material loss rate: High-quality manufacturers should maintain a loss rate of ≤2% (industry average: 3–5%)
Procurement support: Availability of shared component purchasing services to avoid waste in small-batch procurement
Technical support: Free DFM optimization suggestions to reduce trial production risks
Customer service responsiveness: Ability to provide quotations within 12 hours and real-time order status updates
After-sales assurance: Commitment to unconditional rework for quality issues and provision of warranty services
Positioning: Global one-stop electronic manufacturing service platform; benchmark enterprise for low-volume PCB manufacturing
Founded: 2011
Capacity & technology: Monthly capacity of 150,000 m²; supports 2–64 layer PCB prototypes and 2–58 layer low-volume production; minimum trace/spacing 3/3 mil; laser drilling down to 0.1 mm; via copper thickness ≥20 μm; yield rate 99.7%+
Key services:
Free first-time prototyping for 2–6 layer boards (shipping cost only); RMB 200 engineering fee discount for 6/8-layer boards
Full-chain digital management (MES + ERP + IoT systems) with real-time order tracking
One-stop PCBA services (component sourcing + SMT assembly + functional testing)
Customized laminate options (e.g., Shengyi materials) for high-reliability medical and automotive electronics
Certifications: ISO9001, IATF16949, RoHS, REACH
Target customers: 300,000+ global customers across 5G communications, intelligent vehicles, medical electronics, and more
Positioning: Pioneer of “Internet + PCB smart manufacturing”; cost-optimization expert for low-volume prototyping
Founded: 2011
Capacity & technology: Five digital manufacturing bases (total area of 1,800 mu); supports 2–32 layer low-volume PCBs; minimum trace/spacing 4/4 mil; supports advanced processes such as via-in-pad and thermoelectric separation copper substrates
Key services:
Industry-first “panel pooling” model, reducing small-batch costs by up to 60% (standard prototyping from RMB 50)
12-hour ultra-fast delivery (industry-first); standard lead time of 3–5 days
Intelligent warehousing exceeding 130,000 m² with over 560,000 electronic components available
Self-developed EDA/CAM/DFM software to improve manufacturability during the design phase
Certifications: ISO9001, RoHS, UL
Target customers: 6.2 million+ global engineers, startups, and research institutions; preferred choice for hardware prototyping
Positioning: Leading cross-border low-volume PCB brand; digital intelligent manufacturing platform
Founded: 2013
Capacity & technology: Factory area of 20,000 m²; supports 2–40 layer PCBs; minimum trace/spacing 3/3 mil; full range of surface finishes including HASL, ENIG, and OSP
Key services:
One-minute online quotation and ordering; 12-hour fast shipment; global delivery within 6 days
Big-data center monitoring 14,682 devices in real time; on-time delivery rate of 95%
PCBWay platform serving 200+ countries and over 650,000 overseas customers
Supports customized, high-difficulty orders such as HDI boards and thick copper boards
Certifications: ISO9001, RoHS, CE
Target customers: Cross-border SMEs, overseas R&D teams, and electronic makers
Positioning: Fast-turn low-volume PCB prototyping specialist; high cost-performance option
Founded: 2015
Capacity & technology: Monthly capacity of 30,000 m²; supports 2–24 layer PCBs; minimum trace/spacing 4/4 mil; board thickness 0.4–6 mm; yield rate 99.5%+
Key services:
48-hour expedited prototyping for 2–4 layer boards; standard lead time of 3–7 days
Free DFM review and impedance testing; no minimum order quantity (from 1 board)
Transparent pricing with no hidden fees; material loss rate ≤1.8%
One-stop low-volume PCBA services suitable for rapid iteration during R&D validation
Certifications: ISO9001, RoHS
Target customers: Domestic startups, product R&D teams, and university laboratories
| Manufacturer | Core Strengths | MOQ | Fastest Lead Time | Target Customers |
|---|---|---|---|---|
| Huaqiu PCB | Free prototyping, advanced processes, medical/automotive compatibility | 1 board | 48 hours | Mid-to-high-end R&D, mass production |
| JLCPCB | Lowest cost, one-stop component sourcing | 1 board | 12 hours | Makers, startups |
| PCBWay | Cross-border services, digital ordering | 1 board | 12 hours | Overseas customers, cross-border enterprises |
| Xiaoming Prototype | High cost-performance, fast response | 1 board | 48 hours | Domestic R&D teams, pilot production |
Q1: What is the minimum order quantity for low-volume PCBs in Shenzhen?
A: Most mainstream manufacturers support orders starting from 1 board. Typical low-volume orders range from 1 to 1,000 boards, while some manufacturers can handle medium-volume orders of 1–5,000 boards.
Q2: Can the lead time for low-volume PCB prototyping be expedited?
A: Yes. Leading manufacturers offer expedited services, delivering 4-layer prototypes within 48 hours and 6–8 layer boards within 72 hours, with a small additional rush fee.
Q3: How can quality stability be ensured for low-volume PCBs?
A: Choose manufacturers with full-process quality control systems, including pre-order DFM review, in-process SPI + AOI inspections, and pre-shipment functional testing, along with test reports and warranty commitments.
Q4: Do Shenzhen manufacturers support international shipping?
A: Yes. Most leading manufacturers hold import/export qualifications and support international logistics such as DHL and FedEx, delivering to over 180 countries with customs documentation and clearance support.
With their complete industrial chain, flexible manufacturing capabilities, and strong technical expertise, Shenzhen’s low-volume PCB manufacturers have become the preferred partners for global electronics innovators. Whether for rapid validation during R&D, customized low-volume production, or efficient fulfillment of urgent orders, choosing certified and capable Shenzhen manufacturers—such as Huaqiu PCB, JLCPCB, and PCBWay—can significantly reduce trial-and-error costs and shorten time to market.
If you need help precisely matching manufacturers to your project requirements, feel free to provide details such as PCB layer count, trace width/spacing, and delivery timeline, and we will recommend high-value manufacturing partners for you.
As the core document connecting design intent with manufacturing execution, the PCBA assembly drawing directly determines circuit board assembly accuracy, production efficiency, and product reliability. According to industry statistics, 30% of prototype delays are caused by inconsistencies between assembly drawings and the BOM, while standardized assembly drawings can reduce rework rates by more than 40%.
This article systematically breaks down the six core requirements of PCBA assembly drawings, combining IPC international standards with practical cases, to help engineers, purchasers, and manufacturers avoid risks.
A printed circuit board assembly (PCBA) drawing shows the torque parameters for fastening screws to the enclosure and the precise alignment of the printed circuit board.
Its purpose is to ensure that components are installed or soldered correctly. In addition, if engineers must disassemble or reassemble the product to identify the source of a failure, this drawing serves as a useful reference tool.
Manufacturers usually print the drawing on paper or on the reverse side of a single-sided printed circuit board (PCB), where there is no electrical conduction.
Board type and dimensions: Clearly define the PCB outline, thickness (e.g., 1.6 mm standard board), mounting hole locations, and tolerances (±0.05 mm).
Stack-up structure: Indicate the number of copper layers, dielectric material (e.g., FR-4), solder mask type (e.g., green), and copper thickness (e.g., 1 oz).
BOM linkage: Include component reference designators (R1/C1/U1), model specifications, packages (e.g., 0402 / SOIC-8), quantities, and approved substitutes.
Revision history: Record revision date, change description, and responsible person
(Example: Rev.A 2025-01-01 – Added BGA thermal pads).
Component placement drawing: Mark precise component coordinates (X/Y axis), polarity (diode cathode / IC pin 1), and placement orientation. High-density areas require enlarged views.
Special process notes:
Electrostatic-sensitive devices (ESD): mark “±500 V protection”
Lead-free process: specify “Reflow temperature 260 °C Max”
Conformal coating requirements (e.g., S01-3 coating area)
Jumper wire specifications:
No more than 2 jumper wires per board
Length limits: 6 / 8 / 10 mm
Routed along X–Y axes and fixed every 25 mm
Unified fonts (e.g., Arial 10 pt) and high-contrast color schemes (yellow for copper layers, green for solder mask).
Avoid overlapping lines; provide cross-sectional views for critical areas (e.g., BGA pads).
Use IPC standard symbols (e.g., generic resistor/capacitor symbols) instead of custom symbols.
Reference designators must correspond 1:1 with the BOM, avoiding confusion such as “R10” vs. “R100”.
Mechanical tolerances should be labeled separately (e.g., “Mounting hole diameter φ3.0 ± 0.05 mm”).
Component locations in the assembly drawing match Gerber file coordinates.
Placement orientation matches component datasheets.
Pad dimensions comply with IPC-7351 footprint standards
(e.g., 0402 resistor pad width 0.4 mm).
Ensure no omissions in reference designators, packages, or manufacturer part numbers, for example:
| Ref. | Package | Part Number | Qty | Remarks |
|---|---|---|---|---|
| U1 | QFP-44 | STM32F103C8T6 | 1 | Lead-free compatible |
| C2 | 0603 | 100 nF 16 V | 8 | X7R dielectric |
| Parameter | Recommended Tolerance | Impact of Deviation |
|---|---|---|
| Component placement | ±0.1 mm | Degraded signal integrity |
| Drill diameter | ±0.05 mm | Mechanical assembly interference |
| Solder mask clearance | ±0.07 mm | Short-circuit risk |
Reserve fiducial marks for pick-and-place machines.
Mark heat dissipation areas for high-power components
(e.g., “IC thermal pad ≥ 5 mm²”).
Avoid placing ultra-small packages below 0201 next to large components
(minimum spacing ≥ 1 mm).
Version number (Rev.A / B / C) + date + change description + approver.
Major changes must state:
“Replaces previous Rev.A; all orders shall follow this version.”
Main file in searchable PDF, supplemented by Gerber RS-274X / ODB++.
Include 3D models (STEP / IGES) for mechanical interference checks.
IPC-2581: Unified electronic design data format
IPC-7351: Component land-pattern design specification
GB 4458.1: General requirements for mechanical drawings (domestic projects)
Medical devices: Comply with ISO 13485; indicate biocompatible materials
Military products: Follow QJ / MIL standards; clearly define environmental protection level (e.g., GJB 150A)
| Common Error | Cause | Prevention |
|---|---|---|
| Missing polarity markings | Diodes / capacitors not marked | Clearly mark with “+”, “K”, or arrows |
| Insufficient pad spacing | Stencil aperture accuracy not considered | Reserve ≥ 0.2 mm spacing per IPC-2221 |
| Excessive jumper wires | Poor routing design | Optimize PCB stack-up; ≤ 2 jumpers, ≤ 10 mm |
| Version confusion | Revision records not updated | Use cloud-based version control (e.g., Altium 365) |
| Tombstoning | Uneven solder paste / asymmetric pads | Symmetrical pad design; solder paste volume deviation ≤ 10% |
Altium Designer: Built-in IPC compliance checks
Valor NPI: Simulates SMT production to identify manufacturability risks
Export Pick-and-Place files from Altium, use Excel VLOOKUP to link footprint-to-pin-count tables, and automatically calculate total solder joints
(Example formula: =VLOOKUP(@Footprint, PinCountTable, 2, FALSE))
Pre-set IPC-compliant layers, annotation styles, and BOM formats to reduce repetitive work
A qualified PCBA assembly drawing is not only an accurate expression of design intent but also a guarantee of manufacturing efficiency. By following the above requirements, first-pass yield can be increased by more than 22%, while also building trust and collaboration with manufacturers.
If you encounter specific issues in assembly drawing design (such as high-density PCB layouts or special component annotations), feel free to leave a comment—we provide free compliance evaluations.
In today’s rapidly evolving electronics industry, PCB reverse engineering has become an essential approach in electronic R&D, product maintenance, and technological innovation. Whether for redesigning discontinued products, conducting competitive analysis, or upgrading and maintaining legacy equipment, PCB reverse engineering plays an irreplaceable role. This article systematically explains the operational guide of PCB reverse engineering from […]
In today’s rapidly evolving electronic manufacturing industry, new product development cycles are continuously shortening, demand for customization keeps increasing, and the threshold for market validation is gradually rising. Small-batch SMT assembly has evolved from a “supplementary production mode” into a “core support link” for innovative enterprises. Whether it is prototype verification for startups, customized orders for mature enterprises, or market trials for technological products, small-batch processing—thanks to its key advantages of flexible adaptation, controllable costs, and rapid response—has become a critical bridge connecting design concepts with actual mass production.
This article provides a comprehensive breakdown of the core logic and practical key points of small-batch SMT assembly, covering definition analysis, full-process decomposition, quality control, cost optimization, application cases, and service provider selection. It aims to offer standardized consideration and process references for technical personnel while helping decision-makers identify efficient collaboration paths, enabling enterprises to seize opportunities in R&D and production in a fast-changing market.
Small-batch SMT assembly usually refers to PCBA assembly services with a single production volume of 10–5,000 sets, primarily suited for three scenarios: new product R&D prototyping, customized production, and market validation. Compared with mass production, its core advantages include:
Flexibility: Supports rapid design iteration, reducing line changeover and adjustment time by more than 30%.
Cost Control: Eliminates the need for large upfront equipment investments, lowering R&D entry barriers for startups.
Response Speed: Average delivery cycles are 2–3 times faster than mass production, meeting the needs of rapid market validation.
Required files: Gerber files (including all layers), BOM list (clearly specifying part numbers / packages / reference designators), and placement drawings (accurately marking component locations).
Design review points: Pad spacing ≥ 0.3 mm; routing density must meet pick-and-place machine compatibility requirements to avoid short-circuit risks caused by design defects.
Practical recommendation: Use IPC-2221 standards for PCB design and confirm process compatibility with the assembly manufacturer in advance.
Procurement strategy: Prioritize original manufacturers or authorized distributors that support small-batch supply; establish an alternative component library to mitigate material shortages.
Incoming inspection: Verify component polarity and package consistency; focus on electrostatic protection status for sensitive components such as BGAs and ICs.
Cost optimization: Reduce inventory holding costs through a JIT (Just-In-Time) material delivery model.
Prototype verification: Produce 5–10 prototype boards before mass production to test design feasibility.
Board material selection: Use FR-4 for standard products; choose Rogers materials for high-temperature applications.
Surface finish: Prefer HASL or ENIG processes to improve pad wettability.
| Process | Process Parameter Standards | Key Equipment | Quality Control Points |
|---|---|---|---|
| Solder paste printing | Stencil thickness 0.12–0.15 mm, squeegee pressure 50–150 N | High-precision screen printer + SPI inspection | Solder paste thickness tolerance ±15 μm, no bridging |
| Component placement | X/Y axis positioning accuracy ±0.03 mm, rotation accuracy ±0.5° | High-speed pick-and-place + multifunction placement machines | Component offset ≤ 25% of pad width |
| Reflow soldering | Lead-free peak temperature ≤ 260°C, ramp-up rate ≤ 3°C/s | Reflow oven (with temperature profile control system) | Solder joint wetting angle ≤ 40° (Class 3) |
| Post-processing | Water-based cleaning + ultrasonic cleaning | Cleaning machine + ESD-safe packaging equipment | Flux residue ≤ 5 μg/cm² |
In-line inspection: SPI (100% solder paste inspection) + AOI (component placement and soldering defect detection), with false detection rates controlled below 2%.
Specialized inspection: X-ray inspection for BGA packages to ensure void ratios below 15%.
Functional verification: ICT in-circuit testing combined with burn-in testing to simulate real-world usage scenarios and verify electrical performance.
Standards compliance: Strict adherence to IPC-A-610 electronic assembly acceptance standards, with judgment criteria defined according to product class (Class 1–3).
Use modular pick-and-place machines that support SMED (Single-Minute Exchange of Die) quick changeover modes, reducing line changeover time to within 15 minutes.
Desktop reflow ovens are better suited for small-batch production, reducing energy consumption by 40% compared with large-scale equipment.
Apply nano-coating technology to SMT stencils to reduce release residue and lower rework rates.
Customized temperature profiles: implement four-stage temperature control based on PCB layer count and component heat resistance.
Establish a real-time inventory sharing system, enabling suppliers to deliver materials precisely according to production schedules.
Maintain a backup stock rate of ≥80% for commonly used components to mitigate sudden material shortage risks.
Upon receiving an application for SMT small-batch trial production
(Applying departments: R&D, Quality, Purchasing, PE)
Applications for new product trial production and design engineering changes are submitted by the R&D department.
Verification of new material replacements that have previously been mass-produced is requested by the Purchasing department.
Incoming material improvement and experimental verification are proposed by the Quality department, which also follows up on trial production.
Experimental verification initiated by the PE department is applied for by the PE department.
For verification of SMT small-batch trial production of non-finalized products, the Material Control department convenes R&D, Engineering, Quality, Marketing, Purchasing, and other relevant departments to review progress status, material assurance, process assurance, and production process control. Responsibilities and specific timelines are clarified, meeting minutes are generated, and each department implements the decisions accordingly. The Material Control department is responsible for process follow-up and confirmation.
After the requesting department completes the “Small-Batch SMT Trial Production Application Form”, and after the Marketing department provides order status feedback and the Plant Manager/General Manager reviews and approves the application, copies are distributed to R&D, PE, Quality, Material Control, Purchasing, Production, Marketing, and the Plant Manager/General Manager.
Upon receiving the approved “Small-Batch SMT Trial Production Application Form”, the Material Control department promptly issues a Material Requisition Form to the Purchasing department for material ordering.
After receiving the planned Material Requisition Form, the Purchasing department must place orders promptly based on the approved small-batch quantity.
Once all product materials are fully prepared, the Material Control department issues a Production Instruction Order to prepare for small-batch trial production. The typical trial production quantity is 200–500 PCS.
Prior to small-batch trial production of new products, the R&D department prepares production samples and distributes them to the PE, Quality, and Production departments, and organizes a pre-trial production meeting.
After receiving the Small-Batch SMT Trial Production Application Form, the responsible R&D project engineer inspects and tracks all relevant items according to the application content.
Upon receiving the Production Instruction Order issued by Material Control, the Production department begins material preparation (material picking) for small-batch trial production.
After receiving the Production Instruction Order, production personnel manufacture the first article based on the production samples provided by R&D and complete the First Article Inspection Record. Mass trial production begins after first article approval. Any issues arising during SMT trial production are promptly reported to the responsible project engineer and the R&D project leader for resolution. After semi-finished product production is completed, qualified products are warehoused, and SMT production data is submitted to the responsible project engineer.
R&D Prototyping: A smart home company rapidly completed thermostat prototype verification through small-batch processing, completing three design iterations within three months and reducing the R&D cycle by 50%.
Customized Production: An IoT sensor manufacturer adopted small-batch services to customize over 20 products for customers across different industries, with single order quantities of 500–1,000 units, achieving a 30% cost reduction.
Market Validation: A consumer electronics brand produced 1,000 units of a new product via small-batch production for market testing, optimized the design based on feedback, and then proceeded to mass production, avoiding large-scale production risks.
Intelligence: MES systems combined with AI algorithms enable dynamic optimization of process parameters, increasing yield rates to over 99.5%.
High Precision: Support for 01005 ultra-small component placement to meet high-density PCB assembly requirements.
Green Manufacturing: Lead-free solder and environmentally friendly cleaning agents fully replace traditional processes, reducing VOC emissions.
Technical Capability: Availability of a full set of SPI/AOI/X-Ray inspection equipment and compliance with placement accuracy requirements.
Quality System: Certification to ISO 9001 and IPC-A-610 standards, with defect rates controlled below 0.3%.
Response Speed: Design confirmation cycle ≤ 24 hours; urgent order delivery cycle ≤ 3 days.
Service Capability: Provision of one-stop services from design consultation to after-sales rework and repair.
The core value of small-batch SMT assembly lies in enabling enterprises to rapidly verify product feasibility during the R&D stage and gain a competitive edge in the market through “flexible adaptation, precise control, and efficient delivery.” Choosing partners with strong technical expertise and service awareness not only reduces production risks but also allows enterprises to focus their R&D resources on core innovation.
Whether for prototype development by startups or customized production by mature enterprises, small-batch SMT assembly will continue to serve as a key pillar of the electronic manufacturing industry. In the future, as intelligent and green manufacturing technologies advance, its application scenarios within the electronics sector will continue to expand.
In an era marked by accelerated iteration in consumer electronics, widespread adoption of the Industrial Internet of Things (IIoT), and intelligent upgrades in automotive electronics, standardized manufacturing can no longer meet enterprises’ core demands for product differentiation, rapid time-to-market, and controllable costs.
Custom Electronic Manufacturing Services (CMS), as a critical bridge between design concepts and mass production, are becoming a key choice for startups seeking to lower R&D barriers, traditional enterprises optimizing capacity structures, and technology companies accelerating innovation cycles.
This article builds a comprehensive and practical guide to custom electronic manufacturing services from the perspectives of core concepts, supplier selection criteria, operational processes, cost control, risk mitigation, and industry trends. Whether for startup teams requiring small-batch prototyping or mature enterprises pursuing large-scale cooperation, readers can find solutions tailored to their needs and achieve seamless integration from “custom requirements” to “high-quality delivery.”
Custom electronic manufacturing services refer to manufacturers providing end-to-end, personalized solutions based on customer-supplied drawings, samples, or Bills of Materials (BOM). These solutions cover component sourcing, PCB fabrication, SMT assembly, DIP insertion, finished product testing, and after-sales support.
The core value of CMS lies in breaking the limitations of standardized production to accommodate non-standardized requirements across multiple sectors, including consumer electronics, automotive electronics, medical devices, and industrial control—particularly suitable for enterprises requiring rapid iteration or small-batch trial production.
Core Service Scope:
Basic Manufacturing: PCB prototyping/mass production (2–100-layer precision boards), SMT assembly (supporting 01005 packages, BGA pitch down to 0.3 mm), DIP insertion and soldering
Value-Added Services: Component procurement, Design for Manufacturability (DFM) optimization, Electromagnetic Compatibility (EMC) solutions, reliability testing (high/low temperature, salt spray tests)
Full-Process Services: Seamless transition from prototype validation → small-batch trial production → large-scale mass production
In-house Production Capability: Priority should be given to manufacturers capable of completing all processes independently to avoid quality risks caused by outsourcing (e.g., Wuxi Weihongji Electronics achieves full in-house production from PCB to finished product testing).
Equipment Configuration: Key equipment must meet industry standards—high-precision pick-and-place machines (placement accuracy ≥ 0.025 mm), ten-zone nitrogen reflow ovens, online AOI, and X-ray inspection systems.
Process Compatibility: Ability to handle complex processes such as mixed-technology assembly, high-frequency PCBs, and lead-free soldering.
Certifications: Essential international certifications include ISO 9001 (general), IATF 16949 (automotive electronics), and ISO 13485 (medical electronics).
Quality Control Processes: Establish raw material traceability systems and full-process visualized production monitoring, with defect rates controlled below 0.05%.
Testing Capabilities: Comprehensive inspection methods including SPI solder paste inspection, functional testing, and aging tests.
Technical Team: A team of at least 10 R&D engineers capable of providing early-stage technical support such as PCB layout optimization and EMC issue resolution.
Responsiveness: 24-hour technical support, small-batch trial production cycles ≤ 5 days, and on-time delivery rate for urgent orders ≥ 98%.
After-Sales Assurance: Provision of test reports and component lists, with response times for quality issues ≤ 24 hours.
Component Resources: Stable partnerships with well-known brands such as TI, ST, and Murata, with the ability to provide component traceability reports.
Risk Resistance: Backup supplier systems in place to prevent delivery delays caused by component shortages.
Cost Advantage: Bulk procurement can reduce component costs by 20%–30%.
Customer Feedback: Focus on repeat order rates (≥ 75% preferred) and customer retention duration (proportion of customers with over two years of cooperation).
Industry Alignment: Priority given to manufacturers with experience in the same sector (e.g., automotive electronics projects should be handled by providers that have served companies like Lingbo).
On-Site Verification: Conduct on-site audits when necessary to inspect production line management, equipment maintenance, and inspection process standardization.
Requirement Definition: Provide complete PCB design files, BOM lists, and process requirements (e.g., soldering standards, cleanliness requirements).
Confidentiality Agreement: Sign an NDA with the service provider to protect core confidential information such as circuit designs and component models.
Manufacturability Analysis: Request a DFM report from the provider to optimize pad design and component layout, reducing production risks.
Sample Validation: Conduct small-batch trial production (100–500 units) to verify process accuracy and product reliability.
Process Confirmation: Clearly define SMT placement unit pricing, inspection items, and delivery standards to avoid later disputes.
Progress Tracking: Require visualized production progress updates, with timely synchronization at key milestones (e.g., component arrival, first article testing).
Acceptance Criteria: Verify appearance, functionality, and reliability test reports in accordance with certifications such as IATF 16949.
After-Sales Support: Agree on rework procedures for quality issues and response timelines for technical support.
Continuous Optimization: Establish regular communication mechanisms with the service provider to continuously optimize process costs.
| Cost Item | Proportion | Optimization Approach |
|---|---|---|
| Component Procurement | 60%–80% | Choose turnkey services and leverage the service provider’s bulk procurement advantages |
| SMT Assembly Cost | 10%–20% | Unit price for small batches (100–500 units): RMB 2–3 per point; reduced to RMB 0.5–1 per point for large batches (10,000+ units) |
| Testing and Rework | 5%–10% | Early-stage DFM optimization to reduce defect rates |
Pitfall Reminder:
Service providers offering prices below RMB 0.5 per point may pose risks such as component substitution or simplified inspection procedures, which can ultimately result in higher overall costs.
Intellectual Property Risk: Sign confidentiality agreements and clearly define ownership of design files.
Supply Chain Risk: Require the service provider to offer alternative solutions for critical components.
Quality Risk: Select providers with raw material traceability systems and full-process visualized production control.
Delivery Risk: Specify penalties for delayed delivery and prioritize manufacturers with monthly PCBA capacity ≥ 500,000 units.
Telecommunications and data processing are two major application areas of EMS. Knowledge and training in these fields are crucial for preventing technical complexity. Network-based systems are also key considerations within telecommunications applications.
Aerospace and defense sectors extensively implement EMS. Equipment inspection must be conducted without any negligence, and products must be suitable for variable climatic conditions. EMS plays a vital role in aircraft electrification processes as well as military and defense operations.
Industrial operations heavily rely on electronic manufacturing services. These services are designed to support products throughout their entire lifecycle across different global regions. Scope and specifications are key terms associated with industrial control system applications. Additional services include prototype development, inspection, and final assembly.
The medical sector also places high importance on these services. EMS providers are reliable in delivering precise manufacturing processes and advanced technologies while maintaining strict quality benchmarks. When selecting a provider, experience is particularly critical, as customer satisfaction should be the top priority for all services related to this field.
Intelligent Manufacturing: Adoption of Industry 4.0 technologies to enable real-time production data monitoring and automatic optimization of process parameters.
Green Manufacturing: Promotion of lead-free soldering and environmentally friendly materials to comply with global carbon reduction policies.
Flexible Manufacturing: Further reduction of line changeover time to meet rapid iteration demands for multi-variety, small-batch production.
Integrated Services: Expansion from pure manufacturing to full lifecycle solutions encompassing “design + production + after-sales support.”
Selecting a reliable custom electronic manufacturing service provider not only reduces enterprise equipment investment and R&D barriers, but also enables the achievement of three key objectives—rapid time-to-market, controllable costs, and stable quality—through professional process optimization, quality management, and supply chain integration.
The key lies in balancing expertise, pricing, and reputation, avoiding blind pursuit of low prices, and establishing long-term, stable partnerships to jointly drive product innovation and market expansion.
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