There are usually three reasons for the problem of reflow on the PCB: chip interconnection, copper surface cutting, and via jump. The following specific analysis of these factors.

1. Reflow problems caused by chip interconnection

For digital devices, its pin input resistance can be considered infinite, which is equivalent to an open circuit (i = 0 in the figure below). In fact, the loop current is generated by the distributed capacitance and distributed inductance generated by the chip, power supply and ground plane. return. The following takes the collector output circuit as the internal circuit of the output signal as an example for analysis.

1.1 The drive end changes from low level to high level. When the output signal changes from low level to high level, it is equivalent to the output pin outputting a current to the transmission line. Because the input resistance is infinite, we think that for the chip, no current flows in from the input tube leg, then, this The current must return to the power pin of the output chip.

①The signal trace is close to the power plane.
The drive end charges the transmission line formed by the signal trace, the power plane and the terminal load, and the current enters the device from the power supply pin of the drive and flows from the output end of the drive to the load end;
The high-frequency transient return current flows back to the output terminal of the driver on the power plane below the signal trace, and the return current directly passes through the power plane, enters the driver from the power pin of the driver, and forms a current loop.

②The signal routing is close to the ground plane.
The driver charges the transmission line formed by the signal trace, the power plane and the terminal load, and the current enters the device from the power pin of the driver and flows from the output end of the driver to the load end;

The high-frequency transient return current flows back to the output end of the driver on the ground plane below the signal trace. The return current must use the coupling capacitor between the power plane and the ground plane at the output end of the driver to cross from the ground plane to the power plane, and then from the driver The power supply pin of the enters the driver to form a current loop.

1.2 The drive end changes from high level to low level, which is equivalent to the output pin absorbing current on the transmission line.

① The signal trace is close to the power plane.
The load discharges the transmission line formed by the signal trace, the power plane and the output terminal of the driver. The current enters the device from the output pin of the driver, flows out from the ground pin of the driver, enters the ground plane, and passes through the power supply near the ground pin of the driver. The plane and ground plane coupling capacitors cross to the power plane and return to the load end; high-frequency transient return current flows back to the load end on the power plane below the signal traces, forming a current loop.

② The signal routing is close to the ground plane.
The load discharges the transmission line formed by the signal trace, the power plane and the output terminal of the driver, and the current enters the device from the output pin of the driver, flows out of the ground pin of the driver, enters the ground plane, and returns to the load end; high-frequency transient return current Return to the load end on the ground plane below the signal trace, forming a current loop.

Near the output pin and ground pin of the driver, the coupling capacitor between the power plane and the ground plane should be placed to provide a return path for the return current. Otherwise, the return current will find the closest coupling path between the power plane and the ground plane for return flow ( Makes the return path difficult to predict and control, causing crosstalk to other traces).

2. Solutions to reflow problems caused by copper-clad cutting

Ground plane and power plane can reduce the voltage loss caused by resistance. As shown in the figure, the loop current flows back through the ground. Due to the existence of the resistor R1, a voltage drop is bound to occur at points 1 and 2. The greater the resistance, the greater the voltage drop, causing inconsistencies in the ground level. If there is a ground layer, it can be It is regarded as a signal line with infinite line width and low resistance. The loop current always flows through the ground layer closest to the signal. When there is more than one layer in the ground, if the signal is between two ground planes and the two are exactly the same, the loop current will pass through the two planes equally.

2.1. Under the condition of localized layout and wiring, the digital ground plane and the analog ground plane share the same copper-clad plane, that is, the digital ground and the analog ground are not distinguished, and the noise of the digital circuit itself will not bring extra to the analog circuit system. Noise.

2.2. In the digital and analog mixed circuit system, the common location of the digital ground and the analog ground is selected outside the board, that is, the two copper planes are completely independent, so that the signal line between the digital circuit and the analog circuit does not have the characteristics of the transmission line, which brings the system Serious signal integrity issues. The digital circuit and the analog circuit use the same power system, and the ground plane is not divided. In the design of the digital and analog mixed circuit system, on the basis of modular layout and localized wiring, the digital circuit module and the analog circuit module share a complete one. The undivided voltage reference plane not only does not increase the interference of digital circuits to analog circuits, but also eliminates the problem of signal line “cross-channel”, which can greatly reduce the crosstalk between signals and the ground bounce noise of the system, and improve The accuracy of the front-end analog circuit is improved.

3 Solutions to the reflow problem caused by vias

In the signal wiring of the printed board, if it is a multi-layer board, many signals must be changed to complete the connection task. At this time, a large number of vias are used. There are two effects of vias on reflow: one is vias A trench is formed to block the reflow, and the second is the reflow jump layer flow caused by the via hole.

3.1. Trenches formed by vias
In the signal wiring of the printed board, if it is a multilayer board, many signals must be changed to complete the connection task. At this time, a large number of vias are used. If the vias are densely arranged in the power or ground plane, sometimes There will be many vias connected into one piece, forming a so-called groove, as shown in the figure. First of all, we should analyze this situation to see if the reflow needs to pass through the trench. If the signal reflow does not need to pass through the trench, it will not hinder the reflow. If the loop circuit is to bypass this groove and return, the antenna effect formed will increase sharply, causing interference to surrounding signals. Usually, after the coating data is generated, we can adjust the places where the vias are too dense and the trenches are formed, so that a certain distance is left between the vias.

3.2. Layer jump phenomenon formed by vias
Below we take the six-layer board as an example for analysis. The six-layer board has two coating layers, the second layer is the ground layer, and the fifth layer is the power layer. Therefore, the signal reflow of the surface layer and the third layer is mainly in the ground layer; the reflow of the bottom layer and the fourth layer is mainly in the power layer. There are six possibilities for layer wiring: surface layer <-----> third layer, surface layer <-----> fourth layer, surface layer <-----> bottom layer, third layer <--- -->The fourth layer, the third layer <-----> the bottom layer, the fourth layer <-----> the bottom layer, these six possible situations can be divided into two categories according to the loop current situation: If the loop current flows on the same layer and on different layers, that is, whether there is a layer jump phenomenon.

A. The loop current flowing on the same layer includes the surface layer <-----> the third layer, and the fourth layer <-----> the bottom layer, as shown in the figure. In this case, the loop current flows on the same layer. However, according to the principle of electrostatic induction, the internal electric field strength of a complete conductor in an electric field is zero, and all currents flow on the surface of the conductor. The ground plane and the power supply The plane is actually such a conductor. The vias we use are all through holes. The holes left when these vias pass through the power supply and ground plane allow the flow of current on the upper and lower surfaces of the coating layer. Therefore, the return path of these signal lines is very good. , No need to take measures to improve.

B. The situation where the loop current flows on different layers includes the surface layer <-----> the fourth layer, the surface layer <-----> the bottom layer, the third layer <-----> the fourth layer, and the third layer. Layer<----->Bottom layer. Let’s take the surface layer <-----> bottom layer and the third layer <-----> fourth layer as examples to analyze the reflow situation. Signals with layer jump phenomenon need to add some bypass capacitors near the dense area of ​​vias, usually 0.1uf magnetic chip capacitors, to provide a return path.