How can you correctly answer these questions about high-speed PCB?

We often meet various diffrent questions in design pcb, for instance, impedance matching or EMI rules. I’ve sorted some questions and answer about High-speed PCB, hope has some benefit to everybody.

1. How to calculate impedance matching issue at design high-speed PCB schematic layout?

Impedance matching is among the vital factors in designing high-speed PCB circuits. Its have an absolutely relationship with the routing method. For example, whether routing is run microstrip or stripline, with ground layers distance, routing width, PCB material, etc will all influence routings impedance value.

That is to said, impedance values can only be determined after routing. General simulation software can’t consider some impedance non continuous due to circuit model or mathematical algorithms limits. At this moment, these software just pre-left some terminators in the schematic to ease the effect after routing impedance non-continuous, for instance, series resistance, etc.

2. A common method is apart digital and analog when a PCB has several digital and analog modules. That’s why?

The reason for separating the digital/analog ground is because the digital circuit will generate noise on the power supply and ground when the high and low potentials are switched. The noise’s value is related to the speed of the signal and current’s value.

If the ground doesn’t split and the digital circuit generates noise is more, and the analogy area circuit is very close, then even digital and analogy don’t intercourse, the analogy signal still disturbed by ground noise. That is said, digital, analogy and ground doesn’t separate method apply only when the analogy circuit area has a far distance from the digital circuit that generates big noise.

3. what aspects should consider in EMC, and EMI rules when designers do high-speed PCB design?

Generally, designers need to same consider radiated and conducted two aspects in EMI and EMC design. The former is belong to the high frequntly part(>30MHz), the latter is blong to the low frequntly part. So, designers can’t only watch higher frequently and ignore lower frequently.

An outstanding designer who EMI and EMC must consider component location, PCB layer arrangement, important routing, and component choice when the layout at begins.
If these things have no thoughtful pre-plan, then need to spend too much time to fix them, and the cost will soar too.

For example, clock generators location don’t try to approach connector. High speed signal run inner as much as possible, and attention impedance matching and references layers continuous that would be reduced reflections. Component push signal slew rate must be lower as much as possible which should reduce the high-frequency part. Choice decopuling or bypass capacity must attention its frequntly response whether match demand that reduce power plane noise noise.

Others, you must attention to high-frequency signal current loop way and let its return area is lower as much as possible(that is loop impedance is lower) which can reduce radiation. Of course, you can apply a split ground layer to control the high-frequency range. Finally, you should suitable choice for PCB and chassis ground.

4. Is the ground line form a closed circuit to reduce disturbance when designing PCB?

Generally, all designs must reduce loop area that reduces disturbance, when making PCB. Lay ground line, you should design to tree branch shape rather than the close circle. Others, you should amply ground area as much as possible.

5. How do adjust the routing Topology to raise the signal integrity?

This net signal direction is more complicated. It’s hard to say which topology to signal quality has to benefit because it has different influences whether a single, double signal or different voltage level types of signals. And when pre-simulation, needs a high requirement to engineer apply which topology, it requires the designer to know much whether circuit principle, signal type, even routing difficult, etc.

6. How to handle to ensure 100M above signal stabilize in layout and routing?

The high-speed digital signal routing key is to reduce transit line influence to signal. So, it needs signal line routing shortly as much as possible at 100M above high-speed signal layout.
In digital circuits, high-speed signals are defined by signal rise delay time.

Moreover, different signals (TTL, GTL, LVTTL) have different methods to ensure signal quality.